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preliminary 32k/64k/128k x 8/9 synchronous dual-port static ram cy7c09079/89/99 cy7c09179/89/99 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 october 18, 1999 1 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location six flow-through/pipelined devices ? 32k x 8/9 organizations (cy7c09079/179) ? 64k x 8/9 organizations (CY7C09089/189) ? 128k x 8/9 organizations (cy7c09099/199) three modes ? flow-through ?pipelined ?burst pipelined output mode on both ports allows fast 100- mhz cycle time 0.35-micron cmos for optimum speed/power high-speed clock to data access 6.5 [1] /7.5/9/12 ns (max.) low operating power ? active = 195 ma (typical) ? standby = 0.05 ma (typical) fully synchronous interface for easier operation burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes dual chip enables for easy depth expansion automatic power-down commercial and industrial temperature ranges available in 100-pin tqfp pin-compatible and functionally equivalent to idt709079, idt70908, and idt709089 notes: 1. see page 7 for load conditions. 2. i/o 0 ?i/o 7 for x8 devices; i/o 0 ?i/o 8 for x9 devices. 3. a 0 ?a 14 for 32k; a 0 ?a 15 for 64k; and a 0 ?a 16 for 128k devices. logic block diagram r/w l ce 0l ce 1l oe l ft /pipe l i/o 0l ?i/o 7/8l control a 0 ?a 14/15/16l clk l ads l cnten l cntrst l r/w r 1 0 0/1 ce 0r ce 1r oe r 1 0/1 0 ft /pipe r i/o 0r ?i/o 7/8r i/o control a 0 ?a 14/15/16r clk r ads r cnten r cntrst r 1 0 0/1 1 0/1 0 i/o counter/ address register decode true dual-ported ram array counter/ address register decode 8/9 8/9 [2] [2] [3] [3] 15/16/17 15/16/17 for the most recent information, visit the cypress web site at www.cypress.com
cy7c09079/89/99 cy7c09179/89/99 2 preliminary functional description the cy7c09079/89/99 and cy7c09179/89/99 are high- speed synchronous cmos 32k, 64k, and 128k x 8/9 dual- port static rams. two ports are provided, permitting indepen- dent, simultaneous access for reads and writes to any location in memory. [4] registers on control, address, and data lines allow for minimal set-up and hold times. in pipelined output mode, data is registered for decreased cycle time. clock to data valid t cd2 = 6.5 ns [1] (pipelined). flow-through mode can also be used to bypass the pipelined output register to elimi- nate access latency. in flow-through mode data will be avail- able t cd1 = 15 ns after the address is clocked into the device. pipelined output or flow-through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address regis- ter. the internal write pulse width is independent of the low- to-high transition of the clock signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. the use of multiple chip enables allows easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and ut ilize the internal address generated by the internal counter for fast interleaved memory applications. a port ? s burst counter is loaded with the port ? s address strobe (ads ). when the port ? s count enable (cnten ) is asserted, the address counter will increment on each low-to-high transition of that port ? s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. note: 4. when writing simultaneously to the same location, the final value cannot be guaranteed.
cy7c09079/89/99 cy7c09179/89/99 3 preliminary pin configurations notes: 5. this pin is nc for cy7c09079. 6. this pin is nc for cy7c09079 and CY7C09089. 7. for cy7c09079 and CY7C09089, pin #23 connected to v cc is equivalent to an idt x8 pipelined device; connecting pin #23 and #53 to gnd is equivalent to an idt x8 flow-through device. 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 CY7C09089 (64k x 8) cy7c09079 (32k x 8) nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r nc nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc nc i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l nc gnd i/o0r 33 32 31 30 29 28 27 26 cy7c09099 (128k x 8) 100-pin tqfp (top view) [7] [7] [6] [5] [6] [5]
cy7c09079/89/99 cy7c09179/89/99 4 preliminary notes: 8. this pin is nc for cy7c09179. 9. this pin is nc for cy7c09179 and cy7c09189. selection guide cy7c09079/89/99 cy7c09179/89/99 -6 [1] cy7c09079/89/99 cy7c09179/89/99 -7 cy7c09079/89/99 cy7c09179/89/99 -9 cy7c09079/89/99 cy7c09179/89/99 -12 f max2 (mhz) (pipelined) 100 83 67 50 max access time (ns) (clock to data, pipelined) 6.5 7.5 9 12 typical operating current i cc (ma) 250 235 215 195 typical standby current for i sb1 (ma) (both ports ttl level) 45 40 35 30 typical standby current for i sb3 (ma) (both ports cmos level) 0.05 0.05 0.05 0.05 pin configurations (continued) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 cy7c09189 (64k x 9) cy7c09179 (32k x 9) nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc i/o8r i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l i/o8l gnd i/o0r 33 32 31 30 29 28 27 26 cy7c09199 (128k x 9) 100-pin tqfp (top view) [8] [8] [9] [9]
cy7c09079/89/99 cy7c09179/89/99 5 preliminary maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied .. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.3v to +7.0v dc voltage applied to outputs in high z state ................................. ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v latch-up current ...................................................... >200ma pin definitions left port right port description a 0l ? a 16l a 0r ? a 16r address inputs (a 0 ? a 14 for 32k; a 0 ? a 15 for 64k; and a 0 ? a 16 for 128k devices). ads l ads r address strobe input. used as an address qualifier. this signal should be asserted low to access the part using an externally supplied address. asserting this signal low also loads the burst counter with the address present on the address pins. ce 0l ,ce 1l ce 0r ,ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting this signal low resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ? i/o 8l i/o 0r ? i/o 8r data bus input/output (i/o 0 ? i/o 7 for x8 devices; i/o 0 ? i/o 8 for x9 devices). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ? 40 c to +85 c 5v 10% shaded area contains advance information.
cy7c09079/89/99 cy7c09179/89/99 6 preliminary shaded area contains advance information. capacitance note: 10. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 v il and ce 1 v ih ). electrical characteristics over the operating range parameter description cy7c09079/89/99 cy7c09179/89/99 unit -6 [1] -7 -9 -12 min. typ. max. min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v cc =min., i oh = ? 4.0 ma) 2.4 2.4 2.4 2.4 v v ol output low voltage (v cc =min., i oh = +4.0 ma) 0.40.40.40.4v v ih input high voltage 2.2 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com ? l. 250 450 235 420 210 350 195 305 ma ind. 260 445 245 410 225 375 ma i sb1 standby current (both ports ttl level) [10] ce l & ce r v ih , f=f max com ? l. 45 115 40 105 35 95 30 85 ma ind. 55 120 50 110 45 100 ma i sb2 standby current (one port ttl level) [10] ce l | ce r v ih , f=f max com ? l. 175 235 160 220 140 205 125 190 ma ind. 175 235 160 220 140 205 ma i sb3 standby current (both ports cmos level) [10] ce l & ce r v cc ? 0.2v, f = 0 com ? l. 0.05 0.5 0.05 0.5 .05 0.5 0.05 0.5 ma ind. 0.05 0.5 0.05 0.5 0.05 0.5 ma i sb4 standby current (one port cmos level) [10] ce l | ce r v ih , f=f max com ? l. 160 200 145 185 130 170 110 150 ma ind. 160 200 145 185 125 165 ma parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf
cy7c09079/89/99 cy7c09179/89/99 7 preliminary ac test loads (applicable to -6 only) [11] note: 11. test conditions: c = 10 pf. ac test loads (a) normal load (load 1) r1 = 893 ? 5v output r2 = 347 ? c= 30 pf v th =1.4v output c= 30 pf (b) th venin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5v output c= 5pf r th =250 ? (used for t cklz , t olz , & t ohz including scope and jig) v th =1.4v output c (a) load 1 (-6 only) r = 50 ? z 0 = 50 ? 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses 0. 00 0. 1 0 0. 20 0. 30 0. 40 0. 50 0. 60 1 0 1 5 20 25 30 35 (b) load derating curve capacitance (pf) ? (ns) for all -6 access times
cy7c09079/89/99 cy7c09179/89/99 8 preliminary notes: 12. test conditions used are load 2. 13. this parameter is guaranteed by design, but is not production tested. switching characteristics over the operating range parameter description cy7c09079/89/99 cy7c09179/89/99 unit -6 [1] -7 -9 -12 min. max. min. max. min. max. min. max. f max1 f max flow-through 53 45 40 33 mhz f max2 f max pipelined 100 83 67 50 mhz t cyc1 clock cycle time - flow-through 19 22 25 30 ns t cyc2 clock cycle time - pipelined 10 12 15 20 ns t ch1 clock high time - flow-through 6.5 7.5 12 12 ns t cl1 clock low time - flow-through 6.5 7.5 12 12 ns t ch2 clock high time - pipelined 4568ns t cl2 clock low time - pipelined 4568ns t r clock rise time 3333ns t f clock fall time 3333ns t sa address set-up time 3.5 4 4 4 ns t ha address hold time 0011ns t sc chip enable set-up time 3.5 4 4 4 ns t hc chip enable hold time 0011ns t sw r/w set-up time 3.5444ns t hw r/w hold time 0011ns t sd input data set-up time 3.5 4 4 4 ns t hd input data hold time 0011ns t sad ads set-up time 3.5 4 4 4 ns t had ads hold time 0011ns t scn cnten set-up time 3.5 4 4 4 ns t hcn cnten hold time 0011ns t srst cntrst set-up time 3.5444ns t hrst cntrst hold time 0011ns t oe output enable to data valid 8 9 10 12 ns t olz [12, 13] oe to low z 2222ns t ohz [12, 13] oe to high z 17171717ns t cd1 clock to data valid - flow-through 15 18 20 25 ns t cd2 clock to data valid - pipelined 6.5 7.5 9 12 ns t dc data output hold after clock high2222ns t ckhz [12, 13] clock high to output high z 29292929ns t cklz [12, 13] clock high to output low z 2222ns port to port delays t cwdd write port clock high to read data delay 30 35 40 40 ns t ccs clock to clock set-up time 9 10 15 15 ns
cy7c09079/89/99 cy7c09179/89/99 9 preliminary switching waveforms read cycle for flow-through output (ft /pipe = v il ) [14, 15, 16, 17] read cycle for pipelined operation (ft /pipe = v ih ) [14, 15, 16, 17] notes: 14. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 15. ads = v il , cnten and cntrst = v ih . 16. the output is disabled (high-impedance state) by ce 0 =v ih or ce 1 = v il following the next rising edge of the clock. 17. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency
cy7c09079/89/99 cy7c09179/89/99 10 preliminary bank select pipelined read [18, 19] left port write to flow-through right port read [20, 21, 22, 23] notes: 18. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 19. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih . 20. the same waveforms apply for a right port write to flow-through left port read. 21. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 22. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 23. it t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case. switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r
cy7c09079/89/99 cy7c09179/89/99 11 preliminary pipelined read-to-write-to-read (oe = v il ) [17, 24, 25, 26] pipelined read-to-write-to-read (oe controlled) [17, 24, 25, 26] notes: 24. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 25. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 26. during ? no operation, ? data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe
cy7c09079/89/99 cy7c09179/89/99 12 preliminary flow-through read-to-write-to-read (oe = v il ) [15, 18, 24, 25] flow-through read-to-write-to-read (oe controlled) [15, 18, 24, 25] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe
cy7c09079/89/99 cy7c09179/89/99 13 preliminary pipelined read with address counter advance [27] flow-through read with address counter advance [27] note: 27. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 a n t sad t had t scn t hcn t dc t cd1 read external address clk address ads data out cnten q n+3 q n+2 counter hold read with counter read with counter
cy7c09079/89/99 cy7c09179/89/99 14 preliminary write with address counter advance (flow-through or pipelined outputs) [28, 29] notes: 28. ce 0 and r/w = v il ; ce 1 and cntrst = v ih . 29. the ? internal address ? is equal to the ? external address ? when ads = v il and equals the counter output when ads = v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha
cy7c09079/89/99 cy7c09179/89/99 15 preliminary notes: 30. ce 0 = v il ; ce 1 = v ih . 31. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. counter reset (pipelined outputs) [17, 24, 30, 31] switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n
cy7c09079/89/99 cy7c09179/89/99 16 preliminary notes: 32. ? x ? = ? don ? t care, ? ? h ? = v ih , ? l ? = v il . 33. ads , cnten , cntrst = ? don ? t care. ? 34. oe is an asynchronous input signal. 35. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 36. ce 0 and oe = v il ; c e1 and r/w = v ih . 37. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 38. counter operation is independent of ce 0 and ce 1 . read/write and enable operation [32,33,34] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 8 operation x h x x high-z deselected [35] x x l x high-z deselected [35] x l h l d in write l l h h d out read [33] h x l h x high-z outputs disabled address counter control operation [32, 36, 37, 38] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked ? counter disabled x a n h l h d out(n+1) increment counter enabled ? internal address generation
cy7c09079/89/99 cy7c09179/89/99 17 preliminary ordering information 32k x8 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 [1] cy7c09079-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09079-7ac a100 100-pin thin quad flat pack commercial cy7c09079-7ai a100 100-pin thin quad flat pack industrial 9 cy7c09079-9ac a100 100-pin thin quad flat pack commercial cy7c09079-9ai a100 100-pin thin quad flat pack industrial 12 cy7c09079-12ac a100 100-pin thin quad flat pack commercial cy7c09079-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information. 64k x8 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 [1] CY7C09089-6ac a100 100-pin thin quad flat pack commercial 7.5 CY7C09089-7ac a100 100-pin thin quad flat pack commercial CY7C09089-7ai a100 100-pin thin quad flat pack industrial 9 CY7C09089-9ac a100 100-pin thin quad flat pack commercial CY7C09089-9ai a100 100-pin thin quad flat pack industrial 12 CY7C09089-12ac a100 100-pin thin quad flat pack commercial CY7C09089-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information. 128k x8 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 cy7c09099-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09099-7ac a100 100-pin thin quad flat pack commercial cy7c09099-7ai a100 100-pin thin quad flat pack industrial 9 cy7c09099-9ac a100 100-pin thin quad flat pack commercial cy7c09099-9ai a100 100-pin thin quad flat pack industrial 12 cy7c09099-12ac a100 100-pin thin quad flat pack commercial cy7c09099-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information.
cy7c09079/89/99 cy7c09179/89/99 18 preliminary document #: 38 ? 00663 ? e 32k x9 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 cy7c09179-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09179-7ac a100 100-pin thin quad flat pack commercial cy7c09179-7ai a100 100-pin thin quad flat pack industrial 9 cy7c09179-9ac a100 100-pin thin quad flat pack commercial cy7c09179-9ai a100 100-pin thin quad flat pack industrial 12 cy7c09179-12ac a100 100-pin thin quad flat pack commercial cy7c09179-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information. 64k x9 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 cy7c09189-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09189-7ac a100 100-pin thin quad flat pack commercial cy7c09189-7ai a100 100-pin thin quad flat pack industrial 9 cy7c09189-9ac a100 100-pin thin quad flat pack commercial cy7c09189-9ai a100 100-pin thin quad flat pack industrial 12 cy7c09189-12ac a100 100-pin thin quad flat pack commercial cy7c09189-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information. 128k x9 synchronous dual-port sram speed (ns) ordering code package name package type operating range 6.5 cy7c09199-6ac a100 100-pin thin quad flat pack commercial 7.5 cy7c09199-7ac a100 100-pin thin quad flat pack commercial cy7c09199-7ai a100 100-pin thin quad flat pack industrial 9 cy7c09199-9ac a100 100-pin thin quad flat pack commercial cy7c09199-9ai a100 100-pin thin quad flat pack industrial 12 cy7c09199-12ac a100 100-pin thin quad flat pack commercial cy7c09199-12ai a100 100-pin thin quad flat pack industrial shaded area contains advance information.
cy7c09079/89/99 cy7c09179/89/99 19 preliminary package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b

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